Try it in the current lab

Pin this lag run, then raise the pole frequency and compare control effort and final error.

Compare final error and settling with the lead run; inspect where the lag changes phase.

The lab recalculates after a setting changes. Pin a run before changing one variable; the response and control-effort plots share the same replay time. PID experiments also show the P/I/D terms; estimator experiments show measured and estimated states.

What the system is doing

A lag network raises relative low-frequency loop gain. Its pole lies nearer the origin than its zero; the phase penalty and saturation can slow settling.

Connect the design method

Lag places its pole below its zero, increasing relative low-frequency loop gain. Compare the remaining error and settling time. Because the controller has finite DC gain, it cannot promise zero error under a constant load.